The test time that scan tests require typically dominates manufacturing-test costs for integrated circuit designs. The increase in design complexity and the requirements for delay tests have made test time a design parameter that requires active management in nanometer integrated circuit designs. As the number of test patterns increases, it takes more tester-buffer space to hold the complete test set, and it takes longer to execute the test set in manufacturing. To address both the data-volume and test-time problems, rest engineers and test architects have developed techniques employing on-chip hardware that compresses the test-stimulus and response patterns and then applies them to the chip under test.
As an example, The dominant method of testing digital circuits is the use of an automatic test-pattern generator (ATPG) to target a stuck-at or transition fault model at all of the circuit nodes in the integrated circuit. In circuits that contain storage elements, engineers can use scan registers to enable control and observation of the storage elements and ensure high fault coverage. When the ATPG generates too many test patterns, the test-application time becomes too long, and engineers must use on-chip-compression techniques to minimize test time and, thus, test costs.
One compression technique includes the use of multiple input signature registers (MISR) to compress test responses from the circuit under test. The output data from the integrated circuit continually clocks into the MISR, and, at the end of the test, the signature in the MISR assesses a pass or fail versus a known-good signature.